P-channel and n-channel MOS FETs are used together in many prior art integrated circuits. In some of these integrated circuits, the drain of an n-channel FET is connected to the drain of a p-channel FET.
For example, FIG. 1 illustrates a conventional CMOS inverter circuit 100 which includes first voltage supply terminal 101, second voltage supply terminal 102, p-channel FET 103, n-channel FET 104, input terminal 105 and output terminal 106. The drain of p-channel FET 101 is connected to the drain of n-channel FET 102. Certain digital logic circuits, such as NAND and NOR gates, are derived from inverter circuit 100. Consequently, these digital logic circuits also include p-channel and n-channel FETs which have their drains connected.
FIG. 2 shows a conventional six transistor MOS SRAM memory cell 200 which includes first voltage supply terminal 201, second voltage supply terminal 202, word line 203, bit lines 204-205, p-channel load FETs 206-207, cross-coupled n-channel storage FETs 208-209, and n-channel access FETs 210-211. In memory cell 200, the drain of p-channel FET 206 is connected to the drain of n-channel FET 208. Similarly, the drain of p-channel FET 207 is connected to the drain of n-channel FET 209.
FIG. 3 illustrates a cross sectional view of a typical interconnection between p-channel FET 301 and n-channel FET 302. P-channel FET 301 is created from n-type region 310 and includes drain region 311, source region 312 and gate electrode 313. N-channel FET 302 is created from p-type region 320 and includes drain region 321, source region 322 and gate electrode 323. Gate oxide layer 305 is located between gate electrode 313 and n-type region 310, and between gate electrode 323 and p-type region 320. Field oxide region 307 is formed along the upper surface of n-type region 310 and p-type region 320, between drain regions 311 and 321. Insulating layer 306 is located over the complementary transistor structure, with contact openings extending to the source and drain regions of FETs 301 and 302. A metal layer, which includes metal electrodes 331-333, is located over insulating layer 306. Metal electrodes 331 and 333 contact source regions 312 and 322, respectively. Metal electrode 332 contacts drain regions 311 and 321, thereby providing an electrical connection between the drain of p-channel FET 301 and the drain of n-channel FET 302.
Electrical isolation of FETs 301 and 302 is achieved because (1) field oxide 307 and p-type region 320 isolate n-type region 310 and n+ drain region 321 from each other, and (2) field oxide 307 and n-type region 310 isolate p-type region 320 and p+ drain region 311 from each other. However, the physical separation between p+ drain region 311 and p-type region 320, and between n+ drain region 321 and n-type region 310, causes the layout area of FETs 301 and 302 to be relatively large. The typical lateral spacing between p+ drain region 311 and n+ drain region 321 is typically 5-10 .mu.m. Consequently, the configuration illustrated in FIG. 3 is undesirable in a circuit which utilizes a large number of drain-connected p-channel/n-channel FET pairs. For example, the configuration of FIG. 3 is undesirable in a memory device which has a large number of memory cells like SRAM memory cell 200 (FIG. 2).
Additionally, an SRAM memory cell which includes the configuration of FIG. 3 is susceptible to alpha particle upset. Alpha particle upset of MOS FETs in SRAM memory cells is a well-known problem. Alpha particles can cause the state of an SRAM memory cell to change in a random, normally undesirable manner. The alpha particle upset problem becomes increasingly serious as technology advances and transistor dimensions shrink. The sensitivity of SRAM memory cell 200 (FIG. 2) to alpha particles is directly related to the area of the junction between the drains of FETs 206-209 and the underlying substrate. As the area of the junction between the drains and substrate of FETs 206-209 is reduced, the effects of alpha particle upset are also reduced.
The configuration of FIG. 3 also results in undesirable junction capacitances between n-type region 310 and p+ drain 311, and between p-type region 320 and n+ drain 321. The magnitudes of these junction capacitances increase as the area of the junction between n-type region 310 and p+ drain 311 and the area of the junction between p-type region 320 and n+ drain 321 increase. These junction capacitances can reduce the operating speed of certain devices, such as inverter circuit 100 (FIG. 1).
It would therefore be desirable to have a method and structure for connecting the drain of a p-channel FET to the drain of an n-channel FET to create a circuit having a reduced layout area and a reduced junction area between the drains and underlying substrate of the p-channel and n-channel FETS. Such a method and structure would reduce overall circuit layout area, reduce the susceptibility of an SRAM memory cell to alpha particle upset, and minimize the junction capacitance of the circuit.